EquipmentStatus: FOUNDATIONALUpdated 2026-08-24

Semiconductor Wafer Prober

A precision handling and contact system that positions wafer die under a probe interface for electrical test before singulation.

Evidence status

Cites 2 sources, none of which has been read

The sources are named, but none has been retrieved and read as part of building this page. Nothing here has been matched to a passage, so the citations show where a reader might look rather than what was checked.

Rely on this page for

Orientation: how the topic is organised, which terms matter, and where to start reading.

Do not rely on it for

A claim you intend to act on or repeat. Follow the cited material yourself first.

Definition

A wafer prober loads, aligns, thermally conditions, and positions a wafer so that a probe card can contact designated pads or bumps while an automatic test system applies patterns and measurements to each die or test structure.

Process position

Inputs

  • Fabricated wafer
  • Probe card
  • Wafer map
  • Test and temperature recipe

Outputs

  • Tested wafer
  • Die-level bin map
  • Contact and prober telemetry

How it works

  1. 01Load and identify wafer
  2. 02Align wafer and probe card
  3. 03Establish contact and temperature
  4. 04Step through die test sites
  5. 05Generate map and unload

Role in the production flow

The prober is the mechanical, thermal, and positional interface between a full wafer and electrical test. Contact quality can create false failures or damage, so prober, probe card, device pads, and tester must be qualified as one cell.

Interested partyCombines sources[1][2]

A precision handling and contact system that positions wafer die under a probe interface for electrical test before singulation.

Boundary: The cited manufacturers document the equipment category and its intended uses; this record does not independently validate vendor performance claims or rank products.

Qualification and production boundaries

Equipment fit depends on wafer size and thickness, pad or bump geometry, contact technology, temperature range, parallelism, probe force, test-site count, index time, handling risk, and tester integration.

Bounded inferenceMaha inference[1][2]

Equipment fit depends on wafer size and thickness, pad or bump geometry, contact technology, temperature range, parallelism, probe force, test-site count, index time, handling risk, and tester integration.

Boundary: Actual acceptance limits, recipes, throughput, availability, and ownership economics are product-, process-, site-, and contract-specific.

Sources

Citations support the tagged claims above. Access dates record when Maha Strategies last checked the public source.

  1. [1]Semiconductor Production Equipment · Tokyo Electron · accessed 2026-08-13
  2. [2]Technical Briefing: Semiconductor Test · Advantest · 2024 · accessed 2026-08-13

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Direct answer

  • A wafer prober loads, aligns, thermally conditions, and positions a wafer so that a probe card can contact designated pads or bumps while an automatic test system applies patterns and measurements to each die or test structure.

Mechanism and method

  • Load and identify wafer
  • Align wafer and probe card
  • Establish contact and temperature
  • Step through die test sites
  • Generate map and unload

What is measured

  • Alignment accuracy
  • Contact force
  • Planarity
  • Temperature
  • Index time
  • Probe-mark limits
  • Contact-resistance monitoring
  • Probe-mark inspection
  • Planarity calibration
  • Temperature verification
  • Map correlation

Limitations

  • Contact resistance
  • Pad damage
  • Misalignment
  • Thermal nonuniformity
  • Wafer breakage
  • Map-coordinate error

Boundaries declared by the cited sources

  • A product index only. It carries no measured process parameter, no yield or defect data, and no independent comparison, so it cannot support any statement about how a process performs, only about how the vendor organises its catalogue. (boundary declared by Semiconductor Production Equipment)

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