[ Phase 2 // Evidence architecture // Source to strategy ]
Understand the machinery beneath the brief.
Knowledge separates source-governed facts from domain explanations and strategic analysis. Every technical claim carries a citation or an explicit analytical boundary; every article can link back to the immutable facts and Intelligence decisions it supports.
Explore the complete 89-node semiconductor process map →Browse 16 supplier profiles →Universal publication gateway plus governed domain surfaces
50 published semiconductor nodes
16 evidence-bounded supplier profiles
8 lifecycle stages
8 celestial authority contracts
25 Astronomy explainers
41 mathematical concepts · 46 bridges
18 religion methods · 8 comparisons
20 neuromorphic/biocomputing concepts · 8 comparisons
10 governed technical domains · 2 canonical records
Claim-level evidence status
Bidirectional Intelligence links
Recently published integration evidence
ExactZK independent reproduction
A cryptographically signed record that Maha Strategies independently reproduced the expected MNIST MLP verifying-key digests at one pinned ExactZK bundle revision.
Classified as external integration evidence, not canonical domain knowledge. The record states its reproduction boundary and explicit non-claims.
Knowledge domains
Technical knowledge system
Semiconductor manufacturing
A process graph spanning design, materials, equipment, defects, metrology, packaging, suppliers, and supporting Intelligence briefs.
Explore 89 process nodes →
Foundational source layer · celestial-facts/0.1
Celestial facts
A reproducible contract for time, observer, ephemeris, reference frame, corrections, coordinates, and source provenance.
Fact layer only. Explanation and interpretation remain outside this contract.
Inspect 8 authority contracts →
Explanatory layer · astronomy-knowledge/0.2
Astronomy knowledge
A cited graph from observation and calibration through physical models, inference boundaries, and open questions.
Scientific explanation only. Astrological interpretation is outside this layer.
Explore 25 explainers · 21 sources →
Connective grammar · mathematics-knowledge/1.0
Mathematics knowledge
Geometry, time, numerical methods, statistics, networks, and decision procedures connected to each domain through explicit typed records.
Shared mathematics does not transfer scientific validity between physical models and interpretive traditions.
Inspect 41 concepts · 46 bridges →
Methodology layer · religion-knowledge/1.0
Religion and contemplative traditions
Textual authority, translation, historical evidence, lived practice, theology, first-person experience, and empirical claims kept in their proper evidentiary frames.
The system documents and compares claims. It does not rank traditions or certify sacred and metaphysical propositions.
Inspect 18 methods · 8 comparisons →
Substrate-aware technical layer · neuromorphic-biocomputing/1.0
Neuromorphic and biocomputing
Spiking models, neuromorphic hardware, living neural cultures, molecular computation, bioelectronic interfaces, and hybrid systems under separate evidence contracts.
Activity and task performance do not certify consciousness or intelligence; research demonstrations do not imply deployment readiness.
Inspect 20 concepts · 8 comparisons →
Publication gateway · maha-epistemic/1.0
Epistemic publication system
A multi-axis schema, source-rights contract, deterministic provenance hash, and enforceable gate between machine records and public pages.
A record’s existence does not make it publishable. Drafts and incomplete claims remain below the crawlable layer.
Inspect the universal contract →
External evidence · bounded records
Integration evidence
Crawlable reproductions and interoperability records with direct links to signed artifacts, upstream publications and explicit non-claims.
These records document observed integrations. They are not silently promoted into canonical domain knowledge.
Inspect integration evidence →
Governed frontier domain · maha-epistemic/1.0
Quantum systems and advanced energy
Physical architectures, control systems, measurements, models, and readiness boundaries kept separate from formal possibility claims.
Formal mathematics can describe a valid architecture without establishing that a physical implementation is manufacturable, fault tolerant, or commercially ready.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Synthetic biology and cellular engineering
Molecular tools, cell systems, protocols, measurements, and safety boundaries represented with explicit experimental scope.
Performance in a cell line, organoid, animal model, and human intervention are different evidence states and cannot be silently collapsed.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Fusion and plasma systems
Confinement, magnets, plasma control, heat exhaust, fuel cycles, diagnostics, and inertial target systems separated by physical and engineering evidence state.
A plasma-physics result does not establish net electricity, component lifetime, tritium self-sufficiency, maintainability, or commercial plant economics.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Advanced materials
Two-dimensional materials, moiré systems, topological phases, wide-bandgap substrates, interfaces, fabrication, and metrology under specimen-specific contracts.
A property observed in one flake, stack, temperature range, or device geometry cannot be transferred to wafer-scale yield or product performance.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Biomolecular engineering
Protein design, directed evolution, cell-free expression, RNA control, enzyme cascades, and assay provenance separated by experimental system.
A computational design or in-vitro assay result does not establish folding, function, delivery, organism-level safety, or therapeutic benefit.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Longevity and metabolism
Autophagy, mitochondrial respiration, senescence, NAD+ metabolism, nutrient sensing, and intervention endpoints with assay-specific boundaries.
A molecular marker, cell assay, or animal lifespan result cannot be silently converted into a human healthspan or treatment claim.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Neurotechnology and BCI
Neural probes, cortical arrays, optical control, decoding, stimulation, chronic interfaces, telemetry, and translation constraints.
A decoding result in a named participant, task, session, implant, or animal model does not establish durable general-purpose communication or clinical benefit.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Mechanistic interpretability
Features, circuits, interventions, sparse representations, causal tests, and faithfulness criteria represented separately from explanatory confidence.
A human-readable feature label, probe, attention pattern, or ablation effect does not by itself establish a complete or faithful causal explanation.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Agentic systems and MCP
Tool protocols, capability boundaries, sandboxing, context degradation, coordination, deadlock, memory, injection, and evaluation traces.
A successful tool call or benchmark trajectory does not establish least authority, resistance to prompt injection, reliable coordination, or safe autonomous operation.
Open governed domain →
Governed frontier domain · maha-epistemic/1.0
Critical supply chains
Mineral occurrence, refining, precursor chemistry, material substitution, trade concentration, controls, and data uncertainty represented by stage.
Resource abundance, mine output, refining capacity, trade share, and qualified semiconductor supply are different quantities and cannot be silently substituted.
Open governed domain →
Interpretive layer · astrology-traditions/0.3
Astrology traditions
Named interpretive traditions with passage-level provenance from rights-cleared sources, recorded with their disagreements.
Every rule is unvalidated tradition. Provenance is claimed; predictive validity is not, and the schema cannot express it.
Inspect 4 traditions · 125 rules →
Calendrical layer · panchanga/0.1
Pañcāṅga
Tithi, nakshatra, yoga, karaṇa, and vāra computed live from Sun and Moon geometry with a stated ayanāṁśa and flagged boundaries.
Calendar arithmetic only. Whether a moment is auspicious is a tradition claim and is not made here.
Compute for four reference cities →
Compiled verdict · astrology-traditions/0.3
Muhūrta verdict
What the Jyotiṣa tradition holds about a chosen moment, compiled from the pañcāṅga with every source passage attached.
Every withheld rule is shown with its reason, so the reading cannot look stronger than it is.
Compile a moment →
Compiled verdict · natal
Birth pañcāṅga
Janma nakṣatra, tithi, yoga, karaṇa and vāra for a birth moment, with every sourced rule that applies to them.
Not a personality reading. Character, appearance and health rules are withheld by policy and shown as withheld.
Enter a birth moment →
Semiconductor taxonomy
Domain · 1
A system-level map that joins processes, materials, equipment, and decisions.
Process · 18
A manufacturing operation with defined inputs, controls, outputs, and failure modes.
Material · 1
A material family described by function, grade, process exposure, and qualification evidence.
Equipment · 25
A tool class described by process role, control variables, and production constraints.
Concept · 5
A cross-cutting technical idea used across multiple processes or product architectures.
Design
Architecture, logic design, verification, physical implementation, and tape-out.
EDA compute & signoff
Compute, storage, software, and data-management infrastructure used to implement, verify, and sign off an integrated-circuit design before tape-out.
Open technical article →
E-beam mask writer
A direct-write electron-beam system that exposes resist on a mask blank to create the master pattern used by optical wafer lithography.
Open technical article →
Semiconductor manufacturing
A system map of semiconductor design, wafer fabrication, interconnect formation, test, assembly, packaging, and reliability qualification.
Open technical article →
IC design to tape-out
How requirements become architecture, verified logic, physical layout, signoff evidence, and the released database used to make masks.
Open technical article →
Masks and reticles
How signed-off chip layout is corrected, fractured, written, processed, inspected, repaired, and qualified as a lithography reticle set.
Open technical article →
Reticle inspection
An optical or electron-based inspection system used to find pattern, particle, registration, and blank defects before a reticle transfers them to wafers.
Open technical article →
RTL to physical design
The core digital implementation flow from behavioral hardware description to placed, routed, extracted, and signed-off geometry.
Open technical article →
Yield learning & SPC
How measurements, defect maps, equipment history, electrical test, and controlled experiments become process corrections and design feedback.
Open technical article →
Wafer preparation
Crystal growth, slicing, lapping, polishing, cleaning, and incoming-wafer qualification.
Cleanrooms & fab utilities
Why airflow, ultrapure water, gases, vacuum, chemicals, temperature, vibration, and material discipline are part of the semiconductor process.
Open technical article →
Metrology & inspection
How fabs measure dimensions, overlay, films, composition, defects, and electrical behavior without confusing measurement with process control.
Open technical article →
Silicon wafer preparation
How electronic-grade silicon becomes a flat, polished, oriented, and qualified substrate for device fabrication.
Open technical article →
Single-wafer cleaner
A wet-processing system that removes particles, residues, metals, and unwanted films while preparing a controlled wafer surface for the next step.
Open technical article →
Wafer cleaning
How wet, vapor, plasma, and brush cleans remove particles, organics, metals, polymers, oxides, and residues between critical process steps.
Open technical article →
FEOL
Formation of active devices in and on the semiconductor substrate.
ALD reactor
A cyclic deposition reactor that alternates surface-limited precursor exposures to build highly controlled and conformal thin films.
Open technical article →
CMP polisher
A wafer-polishing system that combines controlled mechanical contact and slurry chemistry to remove topography and expose a planar process surface.
Open technical article →
CVD reactor
A thermal or plasma-assisted reactor that forms solid films on wafers through controlled chemical reactions of vapor-phase precursors.
Open technical article →
Thermal processor
A batch or single-wafer thermal system used for oxidation, diffusion, annealing, deposition, and controlled changes to semiconductor materials.
Open technical article →
DUV immersion scanner
A projection lithography system that uses deep-ultraviolet light and immersion fluid to transfer reticle patterns into wafer photoresist at production scale.
Open technical article →
E-beam defect review
A scanning electron-beam system used to image, classify, and sometimes detect wafer defects at higher spatial resolution than production optical inspection.
Open technical article →
EUV lithography scanner
A reflective projection lithography system using 13.5-nanometer extreme-ultraviolet light to pattern advanced semiconductor layers.
Open technical article →
Ion implantation & annealing
How ion dose, energy, angle, masking, lattice damage, and thermal activation create electrically active semiconductor regions.
Open technical article →
Optical wafer inspection
A high-throughput optical system that detects and maps defects on patterned wafers for process monitoring and yield learning.
Open technical article →
Patterning metrology
Optical or electron-based measurement equipment used to quantify layer alignment, feature dimensions, film thickness, and related process variation.
Open technical article →
Photolithography
How coating, alignment, exposure, baking, development, masks, optics, and process control create patterned resist for semiconductor fabrication.
Open technical article →
Coat/develop track
An automated wafer system that coats photoresist, applies thermal treatments, develops exposed images, and interfaces with a lithography scanner.
Open technical article →
Plasma etch system
A vacuum plasma system that selectively removes material to transfer patterns or sculpt semiconductor structures.
Open technical article →
Plasma etch
How wet, dry, plasma, selective, and atomic-layer etch remove material while controlling depth, profile, selectivity, damage, and residues.
Open technical article →
PVD sputter system
A vacuum deposition platform that forms metal and related thin films by ejecting material from a target and transporting it to the wafer.
Open technical article →
Ion implanter
An accelerator and beamline system that introduces controlled dopant or modifying species into a wafer with selected dose and energy.
Open technical article →
Thermal processing
How controlled temperature and atmosphere grow oxide, diffuse species, anneal films, drive reactions, and stabilize wafer structures.
Open technical article →
Thin-film deposition
How semiconductor fabs create conductive, insulating, barrier, liner, and functional films using PVD, CVD, ALD, and related methods.
Open technical article →
MEOL
Contacts and local interconnects that connect transistors to the wiring stack.
BEOL
Multilevel metal and dielectric wiring that connects devices into circuits.
Wafer test
Electrical screening, defect learning, wafer sort, thinning, and singulation preparation.
Advanced packaging
How substrates, RDL, interposers, TSVs, fan-out, chiplets, memory stacks, assembly, test, and thermal design become one system.
Open technical article →
Dicing & singulation
Precision cutting or laser-processing equipment that separates a wafer or package panel into individual die or devices.
Open technical article →
Automatic test equipment
A programmable measurement system that applies electrical stimuli, captures responses, and bins semiconductor devices against defined test limits.
Open technical article →
Wafer prober
A precision handling and contact system that positions wafer die under a probe interface for electrical test before singulation.
Open technical article →
Wafer sort
How process-monitor structures and individual die are electrically probed before assembly, generating parametric evidence and known-good-die candidates.
Open technical article →
Wafer backgrinder
Precision equipment that thins a processed wafer from the backside and may polish the surface to reduce damage and control final thickness.
Open technical article →
Thinning & dicing
How finished wafers are protected, back-ground, stress-relieved, singulated, inspected, picked, and transferred without damaging thin die.
Open technical article →
Assembly & packaging
Die interconnection, protection, system integration, thermal paths, and package formation.
Chip & wafer bonding
Precision alignment and bonding equipment used to join singulated die to wafers or to join prepared wafers in advanced three-dimensional integration flows.
Open technical article →
Die & flip-chip bonder
Precision assembly equipment that picks, aligns, places, and bonds semiconductor die to leadframes, substrates, wafers, or other die.
Open technical article →
Direct-to-silicon cooling
How backside microchannels, manifolds, seals, coolants, flow control, inspection, and serviceability change AI-chip thermal management.
Open technical article →
Substrates & RDL
How organic substrates, interposers, and redistribution layers fan dense die connections into package-scale power, signal, and board interfaces.
Open technical article →
Encapsulation & molding
Packaging equipment that dispenses or transfers protective polymer around assembled semiconductor die and interconnects.
Open technical article →
Underfill & encapsulation
How polymeric materials fill interconnect gaps, redistribute stress, protect die and wires, and become a permanent part of package reliability.
Open technical article →
Wire bond & flip chip
How die are attached and electrically connected by fine wires or area-array bumps, and why each architecture creates different process windows.
Open technical article →
Final test & reliability
Package test, system-level test, qualification, failure analysis, and field feedback.
Burn-in & SLT equipment
Thermal, electrical, and workload equipment used to stress packaged devices and test them under extended or system-representative conditions.
Open technical article →
Final test & burn-in
How packaged devices are screened, characterized, binned, stressed, and exercised in increasingly system-like conditions before shipment.
Open technical article →
Reliability & failure analysis
How products are stressed, monitored, statistically interpreted, dissected, and improved before release and after field failures.
Open technical article →