ProcessStatus: FOUNDATIONALUpdated 2026-08-13

Photolithography: How Circuit Patterns Are Printed on a Wafer

How coating, alignment, exposure, baking, development, masks, optics, and process control create patterned resist for semiconductor fabrication.

Evidence status

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Definition

Photolithography uses light, projection optics, a reticle, and a photosensitive resist to define where later deposition, etch, implant, or clean steps may act on a wafer.

Process position

03 · FEOL04 · MEOL05 · BEOL

Inputs

  • Clean wafer with the target film stack
  • Photoresist and supporting coat materials
  • Reticle or mask
  • Exposure recipe
  • Developer and rinse chemistry

Outputs

  • Patterned resist
  • Overlay and critical-dimension measurements
  • Wafer disposition for pattern transfer

How it works

  1. 01Prepare the wafer surface
  2. 02Spin coat resist and control edge bead
  3. 03Bake the resist
  4. 04Align wafer and reticle
  5. 05Expose the field pattern
  6. 06Post-exposure bake where required
  7. 07Develop, rinse, and dry
  8. 08Inspect critical dimension, overlay, and defects

Process control profile

Materials, equipment, defects, and metrology

These records connect a physical input and tool module to its failure mechanism, detection method, and release decision. They complement the broader inventories in the control surface.

Material focus

Photoresist system

Creates the radiation-sensitive imaging layer and development contrast.

Control: Control solids, solvent balance, filtration, shelf life, coat thickness, bake history, and airborne molecular contamination.

Failure link: Incorrect chemistry or condition shifts dose-to-size, residue, adhesion, or collapse margin.

Equipment module

Scanner and coat/develop track

Coats, bakes, aligns, exposes, develops, rinses, and dries each patterned layer.

Control variables: Dose, focus, leveling, alignment, bake temperature, dispense, spin, and developer timing.

Integration risk: Scanner, track, reticle, resist, and downstream etch must be qualified as one patterning module.

Defect mechanism

Overlay or critical-dimension excursion

Misalignment, focus-dose error, resist variation, or imaging/process interaction moves printed geometry outside its window.

Detection: Overlay metrology, CD-SEM, and patterned-wafer inspection.

Downstream effect: Can create opens, shorts, leakage, or reduced device and interconnect margin.

Metrology gate

CD and overlay metrology

Measures printed feature size and layer-to-layer placement.

Release decision: Rework, hold, continue, or adjust the process based on layer-specific control limits.

Limitation: Sampling can miss localized defects; measurement bias and tool matching must be controlled.

Projection creates a latent image

A scanner projects the reticle pattern through an optical system and focuses it into a photosensitive resist. The wafer stage repeats the exposure across fields while alignment systems manage the relationship between the new layer and structures already present.

EstablishedRestates source[1]

A lithography scanner projects a reticle pattern through optics onto photosensitive material on a wafer.

EstablishedRestates source[3]

After exposure, baking and development remove selected resist regions to create openings for later process steps.

Resolution is a system property

Printed feature size is not determined by wavelength alone. Numerical aperture, process factor, resist behavior, mask correction, focus, exposure dose, and later pattern-transfer steps determine whether a nominal image becomes a usable device feature.

Method basisRestates source[2]

The Rayleigh relationship links printable critical dimension to wavelength, numerical aperture, and a process-dependent factor.

Boundary: The relationship is a resolution framework, not a complete predictor of production yield or pattern fidelity.

Sources

Citations support the tagged claims above. Access dates record when Maha Strategies last checked the public source.

  1. [1]Lithography principles · ASML · accessed 2026-08-13
  2. [2]The Rayleigh criterion for resolution · ASML · accessed 2026-08-13
  3. [3]How microchips are made · ASML · accessed 2026-08-13

Public capability landscape

Supplier profiles

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Named companies are research leads based on public evidence. Inclusion does not establish customer qualification, process-of-record status, available capacity, or supplier ranking.

Lithography systems and computational lithography

ASML

Supplies DUV and EUV lithography platforms and supporting technology for projecting reticle patterns onto wafers.

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Wafer-fabrication equipment

Tokyo Electron

Supplies coat/develop, cleaning, thermal-processing, deposition, and etch equipment across wafer fabrication.

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Process control, inspection, and metrology

KLA

Supplies inspection, metrology, review, and yield-analysis systems across reticles, wafers, and packaging.

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Electronic materials and process chemicals

Dow

Supplies electronic-grade glycol ethers and other materials used in semiconductor and packaging formulations.

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Domain

Semiconductor manufacturing

Process

Plasma etch

Material

PPG & polyether derivatives

Direct answer

  • Photolithography uses light, projection optics, a reticle, and a photosensitive resist to define where later deposition, etch, implant, or clean steps may act on a wafer.

Mechanism and method

  • Prepare the wafer surface
  • Spin coat resist and control edge bead
  • Bake the resist
  • Align wafer and reticle
  • Expose the field pattern
  • Post-exposure bake where required
  • Develop, rinse, and dry
  • Inspect critical dimension, overlay, and defects

What is measured

  • Resist thickness and uniformity
  • Focus and exposure dose
  • Overlay
  • Critical dimension
  • Numerical aperture and wavelength
  • Post-exposure chemistry
  • Defectivity and line-edge roughness
  • Overlay metrology
  • Critical-dimension SEM
  • Optical defect inspection
  • Film-thickness measurement
  • Focus-exposure matrix during process development

Limitations

  • Particles and pinholes
  • Focus or dose error
  • Overlay error
  • Resist scumming or footing
  • Pattern collapse
  • Line-edge roughness
  • Edge-bead contamination

Boundaries declared by the cited sources

  • Vendor-authored explanatory material. It reports no measured yield, no process-window numbers, no independent benchmark, and carries no date, so it cannot support a performance claim or a statement about any particular tool generation. (boundary declared by Lithography principles)

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