ASML
Lithography systems and computational lithography
Supplies DUV and EUV lithography platforms and supporting technology for projecting reticle patterns onto wafers.
Evidence status
Rests on the organisation’s own published documentation
The technical statements here come from documents the organisation publishes about itself. They were read and recorded, so what the company says is accurately reported.
Rely on this page for
What an organisation states about its own products, services and declared scope.
Do not rely on it for
Measured performance, reliability, yield, adoption, or any comparison with another supplier. A company describing itself is not an independent test of it.
What public evidence supports
ASML technical material explains reticles, projection optics, scanners, exposure, and resolution relationships.
Evidence boundary
Scanner capability does not establish the production recipe, achievable yield, or installed configuration at a named fab.
Linked process capabilities
The links below show where the documented capability fits in the chip lifecycle. They are not customer or qualification claims.
Process
Masks and reticles
How signed-off chip layout is corrected, fractured, written, processed, inspected, repaired, and qualified as a lithography reticle set.
Process
Photolithography
How coating, alignment, exposure, baking, development, masks, optics, and process control create patterned resist for semiconductor fabrication.
Applied in Intelligence
Briefs using this capability context
These links identify where the supplier’s public capability profile supports an analytical brief. They do not imply endorsement, customer status, or process-of-record qualification.
Intelligence brief
2nm System-on-Chip Design: Process, Power, and Packaging
What the Angstrom Era means for semiconductors: a 2nm SoC analysis covering GAA transistors, backside power delivery, High-NA EUV, and edge-AI design trade-offs.
Intelligence brief
Advanced-Node Foundry Diversification: Readiness and Risk
An intelligence brief on ASIC vendor and CSP strategies for dual-sourcing 2nm and 1.Xnm silicon across Samsung, Intel, and Rapidus to mitigate geopolitical and capacity risks.
Intelligence brief
Rapidus 2nm: Manufacturing Readiness Framework
A quantitative and qualitative assessment of Rapidus achieving steady-state High-Volume Manufacturing (HVM) on 2nm GAA/nanosheet architecture by 2030.
Sources
- [1]Lithography principles · ASML · accessed 2026-08-13
- [2]The Rayleigh criterion for resolution · ASML · accessed 2026-08-13
- [3]How microchips are made · ASML · accessed 2026-08-13
Direct answer
- Supplies DUV and EUV lithography platforms and supporting technology for projecting reticle patterns onto wafers.
Mechanism and method
- ASML technical material explains reticles, projection optics, scanners, exposure, and resolution relationships.
Limitations
- Scanner capability does not establish the production recipe, achievable yield, or installed configuration at a named fab.
What this does not establish
- Scanner capability does not establish the production recipe, achievable yield, or installed configuration at a named fab.