Governed candidate corpus · review pending
Quantum systems and advanced energy
Physical architectures, control systems, measurements, models, and readiness boundaries kept separate from formal possibility claims.
Primary stress point
Formal mathematics can describe a valid architecture without establishing that a physical implementation is manufacturable, fault tolerant, or commercially ready.
Canonical factory depth
22 of 23 governed factory records are active canonical releases. The candidate corpus remains below the public line until each record independently passes exact-hash review and release.
Canonical public layer
Records that passed the gate
Error mitigation versus error correction
A boundary between estimator-bias reduction on noisy circuits and encoded fault detection and correction.
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Quantum hardware benchmark scope
A comparison contract that fixes the circuit family, compiler, calibration snapshot, acceptance statistic, classical baseline, and uncertainty before ranking systems.
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Physical and logical qubits
A distinction between directly controlled physical degrees of freedom and encoded logical information distributed across them.
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Circuit quantum electrodynamics
A superconducting-circuit architecture in which artificial atoms couple to quantized microwave resonator modes.
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Fault-tolerance threshold condition
The conditional claim that increasing code scale can suppress logical failure when physical operations and noise satisfy a code-and-decoder-specific regime.
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Linear-optical quantum computation
A computation model built from single photons, linear optics, photodetection, ancillas, measurement, and feed-forward.
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Neutral-atom optical-tweezer arrays
Reconfigurable arrays in which neutral atoms are trapped, moved, controlled, and measured with optical systems.
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Silicon and quantum-dot spin qubits
Qubits encoded in electron-spin states confined in semiconductor quantum dots and controlled through exchange and local fields.
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Transmon qubit
A superconducting qubit design that trades a weak reduction in anharmonicity for an exponential reduction in charge dispersion as the Josephson-to-charging-energy ratio increases.
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Trapped-ion QCCD architecture
A segmented trapped-ion architecture that transports ions between storage, interaction, and measurement zones.
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Logical-error suppression with code distance
An empirical comparison of encoded-memory error behavior as the size or distance of an error-correcting code changes.
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Quantum volume benchmark
A system-level benchmark based on successfully implementing randomized model circuits of equal width and depth.
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Dispersive superconducting-qubit readout
A measurement mechanism in which a qubit-state-dependent resonator response is inferred without resonantly exchanging an excitation.
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Josephson-junction nonlinearity
The nonlinear circuit element that makes distinguishable superconducting-qubit transitions possible.
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Rydberg-blockade entangling gates
A neutral-atom interaction mechanism in which excitation of one atom shifts nearby Rydberg transitions and conditions multi-atom dynamics.
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Stabilizer and syndrome measurement
Repeated parity measurements that extract error information while preserving the encoded logical state under the code model.
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Cryogenic superconducting control stack
The coordinated refrigeration, microwave generation, attenuation, filtering, amplification, routing, calibration, and readout chain used to operate a superconducting processor.
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Interleaved randomized benchmarking
A randomized-benchmarking variant that alternates a target gate with random reference operations.
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Quantum error correction
Encoding and syndrome-based procedures intended to detect and correct physical errors without directly measuring the protected logical information.
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Quantum error mitigation
Post-processing and circuit-variation methods intended to reduce estimator bias without encoding a protected logical qubit.
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Random-circuit sampling
A benchmark task that samples outputs from pseudo-random quantum circuits and compares them with a defined classical simulation and verification procedure.
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Randomized benchmarking
A sequence-based protocol that estimates average operation error from the decay of randomized gate sequences.
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Surface-code error correction
A local stabilizer-code architecture typically arranged on a two-dimensional lattice with repeated parity checks.
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Below the public line
Draft inventory remains private until canonical release.
The public surface exposes aggregate capacity only. Draft identifiers, titles, routes, claims, source packets, and review blockers are excluded from crawlable pages and registries.
Withheld records
2
Withheld typed edges
1
Domain contract
The registry exposes the boundary, not just the content.
Graph records
25
Typed edges
31
Public canonical
23
Withheld
2
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