TSMC
Semiconductor foundry and advanced packaging
Provides wafer manufacturing, process control, 3D integration, and advanced packaging platforms.
What public evidence supports
TSMC publicly documents manufacturing engineering, quality and reliability, 3DFabric, CoWoS, and direct silicon cooling research.
Evidence boundary
Platform disclosure does not identify customer programmes, package variants, capacity commitments, or achieved production yield.
Linked process capabilities
The links below show where the documented capability fits in the chip lifecycle. They are not customer or qualification claims.
Process
Advanced packaging
How substrates, RDL, interposers, TSVs, fan-out, chiplets, memory stacks, assembly, test, and thermal design become one system.
Process
Substrates & RDL
How organic substrates, interposers, and redistribution layers fan dense die connections into package-scale power, signal, and board interfaces.
Process
Underfill & encapsulation
How polymeric materials fill interconnect gaps, redistribute stress, protect die and wires, and become a permanent part of package reliability.
Applied in Intelligence
Briefs using this capability context
These links identify where the supplier’s public capability profile supports an analytical brief. They do not imply endorsement, customer status, or process-of-record qualification.
Intelligence brief
Southeast Asian Power Semiconductor Manufacturing: Capability and Risk
Assessing Southeast Asia's realistic role in power semiconductor sourcing, evaluating geopolitical risk reduction, OSAT flexibility, and constraints in process control.
Intelligence brief
Direct-to-Silicon Cooling: Integration and Reliability
A reliability and materials framework for direct-to-silicon liquid cooling of AI chips: backside microchannels, sealing, coolants, manifolds, and high-volume qualification.
Intelligence brief
AI Infrastructure Cycles: Capacity, Demand, and Downturn Risk
An architectural assessment of the AI-driven capital expenditure super-cycle, the impending infrastructure digestion phase, and the structural bifurcation of the semiconductor downturn.
Intelligence brief
Advanced-Node Foundry Diversification: Readiness and Risk
An intelligence brief on ASIC vendor and CSP strategies for dual-sourcing 2nm and 1.Xnm silicon across Samsung, Intel, and Rapidus to mitigate geopolitical and capacity risks.
Intelligence brief
Co-Packaged Optics: Integration, Thermal, and Test Boundaries
An operational audit of the manufacturing and economic barriers preventing high-volume package-to-package optical interconnects, focusing on alignment yield, thermal degradation, and testability.
Intelligence brief
Smartphone Application-Processor Packaging: Architecture and Reliability
A decision framework for selecting fan-out, flip-chip, and package-on-package architectures for smartphone application processors, assessing supplier routes, and interpreting reliability evidence without treating a single test threshold as universal.
Intelligence brief
Smartphone Packaging Contracts: Yield, Capacity, and Risk Allocation
A contract-design framework for allocating capacity, materials, assembly, test, yield, quality, and high-value die risk among smartphone AP owners, OSATs, and package-substrate suppliers.
Sources
- [1]Engineering Performance Optimization · TSMC · accessed 2026-08-13
- [2]Quality and Reliability · TSMC · accessed 2026-08-13
- [3]3DFabric: 3D Silicon Stacking and Advanced Packaging · TSMC · accessed 2026-08-13
- [4]CoWoS Advanced Packaging · TSMC · accessed 2026-08-13
Evidence basis
Evidence basis: Official first-party documentation. This page describes the supplier’s own published claims and does not independently verify performance, reliability, yield or comparative advantage.
What the document records
That TSMC publishes a logic node portfolio spanning A12 through 0.18 micrometre, and describes A12 as combining a second-generation backside power rail with a nanosheet transistor.
What it does not establish
The page gives no yield, no defect density and no independently verified performance figure. Its statements about being the first foundry to reach a node are industry-position claims that a company cannot establish about itself and are excluded here. It is undated, so it cannot establish current availability of any node.
Source
Taiwan Semiconductor Manufacturing Company Limited, Logic Technology · Logic Technology node listings · undated page; copyright notice reads 2010 to 2026 · https://www.tsmc.com/english/dedicatedFoundry/technology/logic · inspected 2026-09-02